Hardware Design Interview Questions
Draw a Transmission Gate-based D-Latch?
Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal?
How do you detect a sequence of "1101" arriving serially from a signal line?
Give the truth table for a Half Adder. Give a gate level implementation of the same.
Design a divide-by-3 sequential circuit with 50% duty circle.
Give two ways of converting a two input NAND gate to an inverter.
How do you detect if two 8-bit signals are same?
Give a circuit to divide frequency of clock cycle by two?
What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
What are the different Adder circuits you studied?